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Altera_Forum
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13 years ago

Signal A lag signal B

Hi, I am a newbie to Altera CPLD. I have a signal A and it's compliment signal B. I would want signal B to always lag 1us w.r.t signal A at the rising edge. And signal A lags signal B by...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks for the replies.

@ Kosh271

You have got the timing diagram right.

signals A and B are generated by CPLD, hence they are outputs.

A is dependent on an external event which is periodic most of the time. I can use a fixed pulse width for A.

Tolerance on B can be +/- 10ns. RT and FT time <=15ns.

I do have a external clock into CPLD of 4.6MHz.