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Honored Contributor
Honored ContributorSignal A lag signal B
Hi, I am a newbie to Altera CPLD. I have a signal A and it's compliment signal B. I would want signal B to always lag 1us w.r.t signal A at the rising edge. And signal A lags signal B by...
Altera_ForumHonored Contributor
Honored ContributorIt will hardly work without a FPGA and PLL clock multiply. I presume you know that "wait xx us" implies counting clock cycles.
You don't clearly distinguish between the timing of the "external event" and signal A, although you say signal A is an output of the CPLD. So it's not the same as the external event? If the external event is unrelated to the 4.6 MHz clock (the general case), synchronization jitter must be considered. There's no specification yet.
