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Altera_Forum's avatar
Altera_Forum
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13 years ago

Signal A lag signal B

Hi, I am a newbie to Altera CPLD. I have a signal A and it's compliment signal B. I would want signal B to always lag 1us w.r.t signal A at the rising edge. And signal A lags signal B by...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

if my pulse width is 100us I think I can do the following:

Detect Rising edge of A using D latch and inverter. (any tips?)

wait for 1us

generate signal B = Not A

wait for 98us

Invert B

The above sequence will only be true if A's pulse width is known.