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Altera_Forum
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13 years ago

Signal A lag signal B

Hi, I am a newbie to Altera CPLD. I have a signal A and it's compliment signal B. I would want signal B to always lag 1us w.r.t signal A at the rising edge. And signal A lags signal B by...
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Altera_Forum
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13 years ago

Eddie13 - It sounds like you have the basics worked out.

I'm not entirely sure if you will be able to meet your timing tolerance with your input clock. The clock period is ~217.4 nS, so I would think that even reaching your goal of 1 uS could be difficult.

If A is run thru a register (D-flip flop), you could be roughly 90 nS late on the rising edge. The falling edge (at 99 uS after the rising edge of A) works out quite well lands at a nice even multiple of your clock.