New ContributorS10 IO Pin Slew Rate
we are using a S10 FPGA on our design which one part of design emulates a SPI Slave device. When we run the design by connecting to another SPI Master, we are seeing failure on high frequency (50MHz clock), and from our debug we notice that the SPI Master/Host is driving the Clock and Data pin correctly, however the S10 IO was driving the Data pin at much worse slew rate (slower rising/falling rate), is there any configuration or constrain to improve the IO pin current strength or slew rate to improve the performance?
Diagram below is from oscilloscope capture on the 50MHz frequency. Top of the diagram, THC being our Master/Host that drive the signals, with much better slew rate, compared to the signal that is driven by the S10 FPGA on the lower part of the diagram.
