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BrixtonBan's avatar
BrixtonBan
Icon for New Contributor rankNew Contributor
2 years ago

S10 IO Pin Slew Rate

we are using a S10 FPGA on our design which one part of design emulates a SPI Slave device. When we run the design by connecting to another SPI Master, we are seeing failure on high frequency (50MHz ...
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Generic Io
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,
not much information given yet. IO-standard set for S10 data out (MISO) pin, connection length, load capacitance (PCB, cable, possibly additional intentional load capacitance), any series resistors or filters used,how is voltage probed?

MOSI and SCK don't look really good, by the way.