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BrixtonBan's avatar
BrixtonBan
Icon for New Contributor rankNew Contributor
2 years ago

S10 IO Pin Slew Rate

we are using a S10 FPGA on our design which one part of design emulates a SPI Slave device. When we run the design by connecting to another SPI Master, we are seeing failure on high frequency (50MHz ...
Configuration
Generic Io
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,

Hope my previous comment helped you to resolve your issue. As we did not receive any further comment, closing this case. However, it will still be open for the community users to comment on.


Regards