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Honored Contributor
Honored ContributorReduce Clock Setup and Clock Hold times
Hi there,
I have a state machine witch makes some math operations. The question is how can I reduce the clock setup and hold times, so I can meet my timing requirements? Here is the code of the state machine:module math_synthesis (
input clk20M,
input a, b,
output reg result_out
);
//Math registers
reg dataa_mult, datab_mult,
dataa_add, datab_add,
dataa_sub, datab_sub,
denom_sig, numer_sig;
wire quotient_sig, remain_sig,
result_add, result_sub;
wire result_mult;
//State machine registers:
reg currentState;
//Registers initial:
initial begin
currentState = 4'd0;
end
//States:
parameter
STATE_1 = 4'd0, STATE_2 = 4'd1,
STATE_3 = 4'd2, STATE_4 = 4'd3,
STATE_5 = 4'd4, STATE_6 = 4'd5,
STATE_7 = 4'd6, STATE_8 = 4'd7;
always @(posedge clk20M) begin
case(currentState)
STATE_1: begin
dataa_mult <= a;
datab_mult <= 16'd977;
currentState <= STATE_2;
end
STATE_2: begin
numer_sig <= result_mult;
denom_sig <= 16'd1000;
currentState <= STATE_3;
end
STATE_3: begin
dataa_mult <= quotient_sig;
datab_mult <= 16'd256;
currentState <= STATE_4;
end
STATE_4: begin
dataa_sub <= result_mult;
datab_sub <= 16'd25600;
currentState <= STATE_5;
end
STATE_5: begin
numer_sig <= result_sub;
denom_sig <= 16'd100;
currentState <= STATE_6;
end
STATE_6: begin
result_out <= quotient_sig;
currentState <= STATE_1;
end
endcase
end
math_mult math_mult_inst (
.dataa ( dataa_mult ),
.datab ( datab_mult ),
.result ( result_mult )
);
math_divide math_divide_inst (
.denom ( denom_sig ),
.numer ( numer_sig ),
.quotient ( quotient_sig ),
.remain ( remain_sig )
);
math_add math_add_inst (
.dataa ( dataa_add ),
.datab ( datab_add ),
.result ( result_add )
);
math_sub math_sub_inst (
.dataa ( dataa_sub ),
.datab ( datab_sub ),
.result ( result_sub )
);
endmodule
