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Altera_Forum's avatar
Altera_Forum
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16 years ago

Reduce Clock Setup and Clock Hold times

Hi there, I have a state machine witch makes some math operations. The question is how can I reduce the clock setup and hold times, so I can meet my timing requirements? Here is the code of the st...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

OK, I have one question now :). Does this mean that if I make a PLL clock multiplier, for example 80MHz and if timings are OK at 20MHz they would be OK at 80MHz as well. What I mean is that the synthesis is adjusted to the clock speed and the connection timings will be proportional to 20MHz?

Best regards,

VT