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OK, I have one question now :). Does this mean that if I make a PLL clock multiplier, for example 80MHz and if timings are OK at 20MHz they would be OK at 80MHz as well. What I mean is that the synthesis is adjusted to the clock speed and the connection timings will be proportional to 20MHz?
Best regards,
VT
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Hi,
as long as you have enough register stages defined it should work. Of course there is a limit, because more pipelining also means higher device utilization. I have a small divider
example attached.
Btw. I mixed up some items:
Pipelining: Means that you or the tool puts some additional registers stage in your design.
Your latency changed, the result is some clocks cycles later available.
Retiming: That is an additional feature to speed up your design. With this feature enabled, the synthesis tool tries to move register through your logic in order to improve the clock speed. The latency did not not change. Hopefully your not to confused now. Sorry.
Kind regards
GPK
Honored Contributor
