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Altera_Forum
Honored Contributor
16 years agoReduce Clock Setup and Clock Hold times
Hi there, I have a state machine witch makes some math operations. The question is how can I reduce the clock setup and hold times, so I can meet my timing requirements? Here is the code of the st...
Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- Thanks for the replay. I know I could improve the timing by adding some pipeline but I want to understand on what those timings depend on. May be I should read more about the lower level of the synthesis. Best regards, VT --- Quote End --- Hi, I have a small drawing attached to show you how retiming works . Kind regards GPK