Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Reduce Clock Setup and Clock Hold times

Hi there, I have a state machine witch makes some math operations. The question is how can I reduce the clock setup and hold times, so I can meet my timing requirements? Here is the code of the st...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

--- Quote Start ---

The math functions are asynchronous, generated by Altera's MegaWizard Plug-In.

By the way what does the following warning mean: 

    Warning: Synthesized away the following LCELL buffer node(s):
        Warning (14320): Synthesized away node "math_mult:math_mult_inst|lpm_mult:lpm_mult_component|mult_k3n:auto_generated|le10a"
        Warning (14320): Synthesized away node "math_mult:math_mult_inst|lpm_mult:lpm_mult_component|mult_k3n:auto_generated|le10a"
...
Thanks,

VT

--- Quote End ---

Hi VT,

the warning means that the synthesis engine found logic which could be without changing the design behaviour.

As far as I know, all arithmetic functions supports so-called pipelining. That means that registers stage will be implemented in order to improve the timing. Of course the result will be available some clock cycles later.

I have an example of a divider attached. Maybe it could help you.

Kind regards

GPK