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Altera_Forum's avatar
Altera_Forum
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16 years ago

Reduce Clock Setup and Clock Hold times

Hi there, I have a state machine witch makes some math operations. The question is how can I reduce the clock setup and hold times, so I can meet my timing requirements? Here is the code of the st...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Hi VT,

the warning means that the synthesis engine found logic which could be without changing the design behaviour.

As far as I know, all arithmetic functions supports so-called pipelining. That means that registers stage will be implemented in order to improve the timing. Of course the result will be available some clock cycles later.

I have an example of a divider attached. Maybe it could help you.

Kind regards

GPK

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Thanks for the replay.

I know I could improve the timing by adding some pipeline but I want to understand on what those timings depend on. May be I should read more about the lower level of the synthesis.

Best regards,

VT