hello i do a clock to 24 hours in vhdl. i am using cyclone 2. I do vhdl files, test them with model sim, after that the comipations goes on with warnings, but it do not work on the fpga ? why ? i can not understand please help

Post some code and we can have a look. From what you say, I can only guess that you have use a bad coding style, but without seeing the code I cant say any more.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter_devidor is port ( CLK, RST :in std_logic; devided_clk : inout std_logic -- Q :out std_logic_vector(24 downto 0) ) ; end counter_devidor; architecture beh of counter_devidor is signal QL : std_logic_vector (24 downto 0); begin process(CLK, RST) begin if (RST = '1') then QL <= "1011111010111100001000000"; devided_clk <= '0'; elsif (CLK'event and CLK = '1') then if (QL = "0000000000000000000000000") then QL <= "1011111010111100001000000"; devided_clk <= not(devided_clk); else QL <= QL - 1; end if; end if; end process; --Q <= QL; end beh; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter60seconds is port ( clk, reset: in std_logic; seconds60 : inout std_logic ); end counter60seconds; architecture beh of counter60seconds is signal cnt : std_logic_vector (5 downto 0); --signal sec_sign : std_logic; begin process (clk, reset ) begin if (reset = '1') then cnt <= "111100" ; seconds60 <= '0' ; else if (clk'event and clk = '1') then if (reset /= '1') then if (cnt = "000001") then seconds60 <= not(seconds60); cnt <= "011110"; else cnt <= cnt - 1 ; end if; end if ; end if; end if ; end process; end beh; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter_10_min is port ( CLK, RST :in std_logic; devided_clk_10_sec : inout std_logic; Q_10_min :out std_logic_vector(3 downto 0); numbers_min10 :inout std_logic_vector(3 downto 0); flagFirst : inout std_logic ) ; end counter_10_min; architecture beh of counter_10_min is signal QL : std_logic_vector (3 downto 0); --signal numbers_sec10_sign : std_logic_vector (3 downto 0); begin process(CLK, RST) begin if (RST = '1') then QL <= "1010"; flagFirst <= '0'; -- numbers_sec10 <= "0000"; devided_clk_10_sec <= '0'; elsif (CLK'event and CLK = '1') then if (QL = "0001") then QL <= "0101"; devided_clk_10_sec <= not(devided_clk_10_sec); flagFirst <= '1'; else QL <= QL - 1; end if; end if; end process; --process(CLK, RST, devided_clk_10_sec) begin -- if (RST = '1') then -- numbers_sec10_sign <= "0000"; --elsif (devided_clk_10_sec'event and devided_clk_10_sec='1' ) then --numbers_sec10 <= "0000"; --numbers_sec10_sign <= numbers_sec10_sign +1 ; --end if ; -- end if ; -- end process; Q_10_min <= QL; --numbers_sec10 <= numbers_sec10_sign; end beh; use ieee.std_logic_1164.all ; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counterSixtyMin is port ( clk_in_10_min, reset: in std_logic; q_Sixty_min_7_segment : out std_logic_vector (3 downto 0) ; --q_Sixty_min : out std_logic_vector (2 downto 0) ; q_Sixty_min_Signal : out std_logic; rst : in std_logic ); end counterSixtyMin; architecture arch of counterSixtyMin is signal cnt : std_logic_vector (2 downto 0); signal cnt_7_segnent : std_logic_vector (3 downto 0); begin process (clk_in_10_min, reset , rst ) begin if (reset = '1' or rst = '1') then cnt <= "000" ; cnt_7_segnent <= "0000"; elsif (clk_in_10_min'event and clk_in_10_min = '0') then if (cnt = "101") then cnt <= "000" ; cnt_7_segnent <= "0000"; else cnt <= cnt +1 ; cnt_7_segnent <= cnt_7_segnent+ 1; end if ; end if ; end process; --q_Sixty_min <= cnt; q_Sixty_min_Signal <= cnt(2); q_Sixty_min_7_segment <= cnt_7_segnent ; end arch; library ieee; use ieee.std_logic_1164.all ; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counterTenHours is port ( clk_1_hour , reset: in std_logic; q_10_HOURS : out std_logic_vector (3 downto 0) ; q_10_hoursSignal : out std_logic; rst : in std_logic ); end counterTenHours; architecture arch of counterTenHours is signal cnt : std_logic_vector (3 downto 0); begin process (clk_1_hour, reset , rst) begin if (reset = '1' or rst = '1') then cnt <= "0000" ; elsif (clk_1_hour'event and clk_1_hour = '0') then if (cnt = "1001") then cnt <= "0000" ; else cnt <= cnt +1 ; end if ; end if ; end process; q_10_HOURS <= cnt; q_10_hoursSignal <= cnt(3); end arch;

library ieee; use ieee.std_logic_1164.all ; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counterTo20Hours is port ( clk_10_hour , reset: in std_logic; --q_2_HOURS : out std_logic_vector (1 downto 0) ; q_2_HOURS_7_segment : out std_logic_vector (3 downto 0) ; rst : in std_logic ); end counterTo20Hours; architecture arch of counterTo20Hours is signal cnt : std_logic_vector (1 downto 0); signal cnt_7 : std_logic_vector (3 downto 0); begin process (clk_10_hour, reset, rst ) begin if (reset = '1' or rst = '1') then cnt <= "00" ; cnt_7 <= "0000"; elsif (clk_10_hour'event and clk_10_hour = '0') then if (cnt = "11") then cnt <= "00" ; else cnt <= cnt +1 ; cnt_7 <= cnt_7 +1 ; end if ; end if ; end process; --q_2_HOURS <= cnt; q_2_HOURS_7_segment <= cnt_7 ; end arch; library ieee; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all; entity decoder7seg is port (DIGIT : in std_logic_vector(3 downto 0); SEG : out std_logic_vector(6 downto 0) ); end entity decoder7seg; architecture decoder7seg_a of decoder7seg is begin --decode : process DIGIT is SEG <= "1000000" when DIGIT="0000" else -- 0 "1111001" when DIGIT="0001" else -- 1 "0100100" when DIGIT="0010" else -- 2 "0110000" when DIGIT="0011" else -- 3library ieee; "0011001" when DIGIT="0100" else -- 4 "0010010" when DIGIT="0101" else -- 5 "0000010" when DIGIT="0110" else -- 6 "1111000" when DIGIT="0111" else -- 7 "0000000" when DIGIT="1000" else -- 8 "0010000" when DIGIT="1001" else -- 9 "0001000" when DIGIT="1010" else -- A "0000011" when DIGIT="1011" else -- b "1000110" when DIGIT="1100" else -- C "0100001" when DIGIT="1101" else -- d "0000110" when DIGIT="1110" else -- E "0001110" when DIGIT="1111" else -- F "0000000"; end architecture decoder7seg_a; library ieee; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.numeric_std.ALL; entity clockTop is port ( clk50Mhz : in std_logic; resetTop : in std_logic; tenMinutesOut : out std_logic_vector (6 downto 0); sixtyMinOut : out std_logic_vector (6 downto 0); TenHoursOut : out std_logic_vector (6 downto 0); TwoHoursOut : out std_logic_vector (6 downto 0) ); end clockTop; architecture struct of clockTop is component counter60seconds port ( clk, reset: in std_logic; seconds60 : inout std_logic ); end component; component secondGenerator port ( CLK, RST :in std_logic; devided_clk : inout std_logic -- Q :out std_logic_vector(24 downto 0) ) ; end component ; component counterToTen is port ( clk, reset: in std_logic; q_MIN : out std_logic_vector (3 downto 0) ; q_10_minSignal : out std_logic; rst : in std_logic ); end component; component counterSixtyMin is port ( clk_in_10_min, reset: in std_logic; q_Sixty_min_7_segment : out std_logic_vector (3 downto 0) ; --q_Sixty_min : out std_logic_vector (2 downto 0) ; q_Sixty_min_Signal : out std_logic; rst : in std_logic ); end component; component counterTenHours is port ( clk_1_hour , reset: in std_logic; q_10_HOURS : out std_logic_vector (3 downto 0) ; q_10_hoursSignal : out std_logic; rst : in std_logic ); end component; component counterTo20Hours is port ( clk_10_hour , reset: in std_logic; --q_2_HOURS : out std_logic_vector (1 downto 0) ; q_2_HOURS_7_segment : out std_logic_vector (3 downto 0) ; rst : in std_logic ); end component; component segment7 port (DIGIT : in std_logic_vector(3 downto 0); SEG : out std_logic_vector(6 downto 0) ); end component; signal reset_sign : std_logic; signal OneSecWire : std_logic ; signal q_line : std_logic_vector(24 downto 0); signal OneMinWire : std_logic; signal q_10_minutes_signal : std_logic_vector(3 downto 0); signal q_10_minSignal_IntSign : std_logic; signal q_Sixty_min_Signal_IntSign : std_logic; signal q_10_HOURS_IntSign_Vector : std_logic_vector (3 downto 0); signal q_10_hoursSignal_IntSign : std_logic; signal q_2_HOURS_7_segment_IntSign : std_logic_vector (3 downto 0); signal q_Sixty_min_7_segment_IntSign : std_logic_vector (3 downto 0); signal rst_signal : std_logic; for ALL: segment7 use entity work.decoder7seg(decoder7seg_a); for ALL : counterTo20Hours use entity work.counterTo20Hours; for ALL : counterTenHours use entity work.counterTenHours; for ALL : counterSixtyMin use entity work.counterSixtyMin; for ALL: counterToTen use entity work.counterToTen; for ALL: secondGenerator use entity work.counter_devidor; for ALL : counter60seconds use entity work.counter60seconds; begin secondGeneratorInst : secondGenerator port map ( clk50Mhz, reset_sign ,OneSecWire ) ; counter60secondsInst : counter60seconds port map (OneSecWire, reset_sign, OneMinWire ) ; counterToTenInst : counterToTen port map ( OneMinWire, reset_sign, q_10_minutes_signal, q_10_minSignal_IntSign, rst_signal ); counterSixtyMinInst : counterSixtyMin port map( q_10_minSignal_IntSign, reset_sign, q_Sixty_min_7_segment_IntSign , --q_Sixty_min : out std_logic_vector (2 downto 0) , q_Sixty_min_Signal_IntSign, rst_signal ); counterTenHoursInst :counterTenHours port map ( q_Sixty_min_Signal_IntSign , reset_sign, q_10_HOURS_IntSign_Vector, q_10_hoursSignal_IntSign, rst_signal ); counterTo20HoursInst: counterTo20Hours port map ( q_10_hoursSignal_IntSign , reset_sign, --q_2_HOURS : out std_logic_vector (1 downto 0) ; q_2_HOURS_7_segment_IntSign, rst_signal ); segment7_10Min : segment7 port map (q_10_minutes_signal, tenMinutesOut); segment7_60Min : segment7 port map (q_Sixty_min_7_segment_IntSign, sixtyMinOut); segment7_10hours : segment7 port map (q_10_HOURS_IntSign_Vector, TenHoursOut); segment7_2hours : segment7 port map (q_2_HOURS_7_segment_IntSign, TwoHoursOut); process (clk50Mhz, resetTop, q_2_HOURS_7_segment_IntSign , q_10_HOURS_IntSign_Vector , q_Sixty_min_7_segment_IntSign , q_10_minutes_signal ) begin if (clk50Mhz'event and clk50Mhz = '1') then if (q_2_HOURS_7_segment_IntSign = "0010" and q_10_HOURS_IntSign_Vector = "0011" and q_Sixty_min_7_segment_IntSign = "0101" and q_10_minutes_signal = "1001" ) then rst_signal <= '1'; end if; end if ; end process; reset_sign <= resetTop; end; that is ... in simulation is ok ... but ot nthe fpga do not works ...

Here is your big problem - you are generating a load of clocks in logic. Dont do that. Generate enable signals instead and run ALL registers from the system clock "clk". also, your derived clocks look at falling edge, and other clocks look for rising edge. Convention is to have all clocks work on the rising edge. For a clock deisgn, you seem to have made it very complicated.

so you tell me that i have a single clock ? how can i reach this ? when 1 min goes the eneable of the counter to 10 min should be on for 1 pulse of the shared single clock ? i am not sure that is your idea ... the fpga module takes 50 mhz clock input - is this the shared clock that i should use or devided clock with T with 1 sec is it good idea to use frequency devidor to reach 1 second T or i shoud use enable ?

problem | Altera Community

13 Replies

Altera_Forum

Honored Contributor

16 years ago


process(clk_50MHz, reset)
begin
  if reset = '1' then
    --reset D
  elsif rising_edge(clk_50MHz) then
    if enable = '1' then --this can be things like "enable minute" or something
      q <= q + 1;
    end if;
  end if;
end process;

Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
Use the 50Mhz clock. Never use derived clocks (unless you use a PLL)

The template you should use for enabled registers is this:

process(clk_50MHz, reset) begin if reset = '1' then --reset D elsif rising_edge(clk_50MHz) then if enable = '1' then --this can be things like "enable minute" or something q <= d; end if; end if; end process;

--- Quote End ---

but how can i do addition with enables ?
Altera_Forum
Honored Contributor
16 years ago
i do this design

counter to 2 <- coutner to 10 <- counter to 6 <- counter to 10

i want to make counter to 24 hours
the counter to 24 works fine
the counter to 60 works fine
whne i connect the two counters it start to work not properly
whne it reach 9 it jumps to 12 ... when it goest to 19 it jumps in 22
when reach 29 i jump to 32
can it be from derived clockes or it is somethin else
how can i solve this problem ?
please help
Altera_Forum
Honored Contributor
16 years ago
The derrived clock wont arrive at each register at the same time.
Altera_Forum
Honored Contributor
16 years ago
what should i understand for "large skews"
Altera_Forum
Honored Contributor
16 years ago
Using normal FPGA logic to create clock signals (ie,clock dividers and clock gates) creates timming problems because those clocks signals often end up with large skews.
Altera_Forum
Honored Contributor
16 years ago
why i can not use derived clock ?

Altera_Forum

Honored Contributor

16 years ago

Use the 50Mhz clock. Never use derived clocks (unless you use a PLL)

The template you should use for enabled registers is this:


process(clk_50MHz, reset)
begin
  if reset = '1' then
    --reset D
  elsif rising_edge(clk_50MHz) then
    if enable = '1' then --this can be things like "enable minute" or something
      q <= d;
    end if;
  end if;
end process;

Altera_Forum
Honored Contributor
16 years ago
so you tell me that i have a single clock ? how can i reach this ?
when 1 min goes the eneable of the counter to 10 min should be on for 1 pulse of the shared single clock ?
i am not sure that is your idea ...
the fpga module takes 50 mhz clock input - is this the shared clock that i should use or devided clock with T with 1 sec
is it good idea to use frequency devidor to reach 1 second T or i shoud use enable ?
Altera_Forum
Honored Contributor
16 years ago
Here is your big problem - you are generating a load of clocks in logic. Dont do that. Generate enable signals instead and run ALL registers from the system clock "clk".

also, your derived clocks look at falling edge, and other clocks look for rising edge. Convention is to have all clocks work on the rising edge.

For a clock deisgn, you seem to have made it very complicated.

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problem

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