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Altera_Forum's avatar
Altera_Forum
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15 years ago

problem

hello i do a clock to 24 hours in vhdl. i am using cyclone 2. I do vhdl files, test them with model sim, after that the comipations goes on with warnings, but it do not work on the fpga ? why...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

Use the 50Mhz clock. Never use derived clocks (unless you use a PLL)

The template you should use for enabled registers is this: 


process(clk_50MHz, reset)
begin
  if reset = '1' then
    --reset D
  elsif rising_edge(clk_50MHz) then
    if enable = '1' then --this can be things like "enable minute" or something
      q <= d;
    end if;
  end if;
end process;

--- Quote End ---

but how can i do addition with enables ?