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Honored Contributor
Honored Contributorproblem
hello i do a clock to 24 hours in vhdl. i am using cyclone 2. I do vhdl files, test them with model sim, after that the comipations goes on with warnings, but it do not work on the fpga ? why...
Altera_ForumHonored Contributor
Honored ContributorHere is your big problem - you are generating a load of clocks in logic. Dont do that. Generate enable signals instead and run ALL registers from the system clock "clk".
also, your derived clocks look at falling edge, and other clocks look for rising edge. Convention is to have all clocks work on the rising edge. For a clock deisgn, you seem to have made it very complicated.
