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Altera_Forum
Honored Contributor
Honored Contributorproblem
hello i do a clock to 24 hours in vhdl. i am using cyclone 2. I do vhdl files, test them with model sim, after that the comipations goes on with warnings, but it do not work on the fpga ? why...
Altera_ForumHonored Contributor
Honored ContributorUsing normal FPGA logic to create clock signals (ie,clock dividers and clock gates) creates timming problems because those clocks signals often end up with large skews.
