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Altera_Forum
Honored Contributor
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hello i do a clock to 24 hours in vhdl. i am using cyclone 2. I do vhdl files, test them with model sim, after that the comipations goes on with warnings, but it do not work on the fpga ? why...
Altera_ForumHonored Contributor
Honored Contributori do this design
counter to 2 <- coutner to 10 <- counter to 6 <- counter to 10 i want to make counter to 24 hours the counter to 24 works fine the counter to 60 works fine whne i connect the two counters it start to work not properly whne it reach 9 it jumps to 12 ... when it goest to 19 it jumps in 22 when reach 29 i jump to 32 can it be from derived clockes or it is somethin else how can i solve this problem ? please help
