Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorproblem
hello i do a clock to 24 hours in vhdl. i am using cyclone 2. I do vhdl files, test them with model sim, after that the comipations goes on with warnings, but it do not work on the fpga ? why...
Altera_ForumHonored Contributor
Honored Contributorso you tell me that i have a single clock ? how can i reach this ?
when 1 min goes the eneable of the counter to 10 min should be on for 1 pulse of the shared single clock ? i am not sure that is your idea ... the fpga module takes 50 mhz clock input - is this the shared clock that i should use or devided clock with T with 1 sec is it good idea to use frequency devidor to reach 1 second T or i shoud use enable ?
