Honored ContributorHello,
I have a system with 2 FPGA's. In each FPGA I need a clock of 40MHz. I can generate it with a PLL in each board. My question is: If the 2 PLL's generate the 40MHz signal from the same xtal, the two outputs will be in phase? Please look the attached image. Thank you.
Honored ContributorClearly no.
Honored ContributorHello,
But they will not be completely asynchronous, because they use the same xtal for generate the output? Can I predict something about the difference of phase? Maybe is clear for you, but I am a beginner. Sorry. Thank you for your answer.Honored Contributorin phase,as asked, involves a fixed relation. Actually they are initialized to an arbitrary phase difference, that should be maintained until a PLL reset or a reconfiguration. The phase difference depends e.g. on the POR timing and shouldn't be expected as stable. A synchronous, reset of both PLLs can possibly achieve a fixed phase relation. If you are using FPGA with dynamic phase shift option (e.g. Cyclone III), you can implement a simple logic, that synchronizes one PLL to another on Init and than freezes this phase relation.
Honored ContributorEr.. Something doesn't make sense here.
ALT_PLL allows one to specify the output clocks' phase shift. One can use PLLs to, for example, generate a clock with the same frequency but shifted by 90º in relation to the source clock. I don't think there's anything arbitrary in it.Honored ContributorYou can't have a fixed phase shift between a source 24MHz clock and a generated 40MHz clock.
If you generated 48MHz instead, then it would be feasible.Honored Contributoryou can try to create one clock on a master FPGA and use it to drive the slave FPGA, then you will have a constant phase difference. but you will need to be careful about interםducing noise on the trace.
Honored ContributorTo answer the question. The clock in both FPGAs, will have the same frequency because the come from the same source. However, the phase in each FPGA will be dependant on several other delays.
For example, if the clock takes longer to get to one FPGA than the other, that will introduce a phase difference. Also, differences in the pin-to-pad delay between the FPGAs will introduce a phase shift. Is the clock connected to the exact same pin on both FPGAs? If not, there will be a phase difference there? Any differences between the two clock paths will result in a phase delay. And you can't guarantee there aren't differences. Now, what you probably could do is to determine a unique PLL phase offset for each FPGA that might get you close enough so that the two were in phase. You haven't actually stated why you need the clock to be in phase between the FPGAs. If you are sending data between the two FPGAs and hoping to use the clock to capture the data between the two, then having them in phase may not be what you want anyway. The data delay between the two parts may be enough that you don't want to capture it with a clock of the same phase. JakeHonored ContributorHonored ContributorI apologize. I didn't look closely enough at the picture nor read the subsequent posts closely enough. I failed to recognize that the 40MHz clocks were being derived from a 24MHz clock (I thought the source clock was 40MHz as well). Under these enlightened circumstances, FvM is most certainly correct. You have no way of knowing when each PLL will start running with regards to the phase of the 24MHz clock.
Sorry, Jake
