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Altera_Forum
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16 years ago

phase between 2 PLL's in different FPGA

Hello, I have a system with 2 FPGA's. In each FPGA I need a clock of 40MHz. I can generate it with a PLL in each board. My question is: If the 2 PLL's generate the 40MHz signal from...
Altera_Forum's avatar
Altera_Forum
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16 years ago

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You can't have a fixed phase shift between a source 24MHz clock and a generated 40MHz clock.

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Yes, the phase relation between both is periodic with 8 MHz, the largest common divisor. Because both FPGA PLLs aren't starting synchronously, the 40 MHz clocks typically have different phase, even if all systematic delays and type dependant variations mentioned by jakobjones won't exist.

In so far, the original question can be answered clearly. Different solutions have been suggested, too.