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Honored Contributor
Honored Contributorphase between 2 PLL's in different FPGA
Hello, I have a system with 2 FPGA's. In each FPGA I need a clock of 40MHz. I can generate it with a PLL in each board. My question is: If the 2 PLL's generate the 40MHz signal from...
Altera_ForumHonored Contributor
Honored ContributorEr.. Something doesn't make sense here.
ALT_PLL allows one to specify the output clocks' phase shift. One can use PLLs to, for example, generate a clock with the same frequency but shifted by 90º in relation to the source clock. I don't think there's anything arbitrary in it.
