phase between 2 PLL's in different FPGA

To answer the question. The clock in both FPGAs, will have the same frequency because the come from the same source. However, the phase in each FPGA will be dependant on several other delays.

For example, if the clock takes longer to get to one FPGA than the other, that will introduce a phase difference. Also, differences in the pin-to-pad delay between the FPGAs will introduce a phase shift. Is the clock connected to the exact same pin on both FPGAs? If not, there will be a phase difference there? Any differences between the two clock paths will result in a phase delay. And you can't guarantee there aren't differences.

Now, what you probably could do is to determine a unique PLL phase offset for each FPGA that might get you close enough so that the two were in phase.

You haven't actually stated why you need the clock to be in phase between the FPGAs. If you are sending data between the two FPGAs and hoping to use the clock to capture the data between the two, then having them in phase may not be what you want anyway. The data delay between the two parts may be enough that you don't want to capture it with a clock of the same phase.

Jake