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Altera_Forum
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16 years ago

phase between 2 PLL's in different FPGA

Hello, I have a system with 2 FPGA's. In each FPGA I need a clock of 40MHz. I can generate it with a PLL in each board. My question is: If the 2 PLL's generate the 40MHz signal from...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I apologize. I didn't look closely enough at the picture nor read the subsequent posts closely enough. I failed to recognize that the 40MHz clocks were being derived from a 24MHz clock (I thought the source clock was 40MHz as well). Under these enlightened circumstances, FvM is most certainly correct. You have no way of knowing when each PLL will start running with regards to the phase of the 24MHz clock.

Sorry,

Jake