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Honored Contributorphase between 2 PLL's in different FPGA
Hello, I have a system with 2 FPGA's. In each FPGA I need a clock of 40MHz. I can generate it with a PLL in each board. My question is: If the 2 PLL's generate the 40MHz signal from...
Altera_ForumHonored Contributor
Honored Contributorin phase,as asked, involves a fixed relation. Actually they are initialized to an arbitrary phase difference, that should be maintained until a PLL reset or a reconfiguration. The phase difference depends e.g. on the POR timing and shouldn't be expected as stable. A synchronous, reset of both PLLs can possibly achieve a fixed phase relation. If you are using FPGA with dynamic phase shift option (e.g. Cyclone III), you can implement a simple logic, that synchronizes one PLL to another on Init and than freezes this phase relation.
