Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

phase between 2 PLL's in different FPGA

Hello, I have a system with 2 FPGA's. In each FPGA I need a clock of 40MHz. I can generate it with a PLL in each board. My question is: If the 2 PLL's generate the 40MHz signal from...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

you can try to create one clock on a master FPGA and use it to drive the slave FPGA, then you will have a constant phase difference. but you will need to be careful about interםducing noise on the trace.