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Honored Contributor
Honored Contributorphase between 2 PLL's in different FPGA
Hello, I have a system with 2 FPGA's. In each FPGA I need a clock of 40MHz. I can generate it with a PLL in each board. My question is: If the 2 PLL's generate the 40MHz signal from...
Altera_ForumHonored Contributor
Honored Contributoryou can try to create one clock on a master FPGA and use it to drive the slave FPGA, then you will have a constant phase difference. but you will need to be careful about interםducing noise on the trace.
