Hello Please guide me why I don't see any logic element for the current code : LIBRARY ieee; USE ieee.std_logic_1164.all; Use ieee.numeric_std.all; USE work.my_data_types.all; -- to define array of input ( package ) ENTITY test IS PORT ( clk: in std_logic; OutResult: out signed(9 downto 0)); end test; Architecture behave of test is Signal Im : Array2D:=(("0010000111","0001111110","0001001101","0000000000","0000000000"), ("0001001111","0010000100","0000101100","0000011011","0000000000"), ("0001011101","0010000100","0000100111","0000101001","0000000000"), ("0001011101","0010000100","0000100111","0000101001","0000000000"), ("0000000000","0000000000","0000000000","0000000000","0000000000")); signal Bufftemp:Array2D; signal Buffsig:signed(9 DOWNTO 0); begin Process (clk) variable i,j:integer range 0 to 7:=0; begin if (clk' event and clk='1') then for j in 0 to 1 loop for i in 0 to 1 loop Bufftemp(2*j,2*i+1)<= Im(2*j,2*i+1) - 5; end loop; end loop; end if; Buffsig<=Bufftemp(i,j); end process; OutResult<=Buffsig; end behave;

This will because buffsig is a constant. i and j are always 0 when assigning buffsig. And all buffsig values are assigned from a constant. So hence the design is reduced to a constant driver.

You misunderstand for loops. The loops are evaluated completely each clock cycle. The code outputs constantly the last array element. No logic cells required.

Thank you very much Tricky and FvM. I am really appreciate your instant help. I figured out a solution to read one element each clock cycle as listed as I see it best solution Process (clk) variable i,j:integer range 0 to 7:=0; begin i:=i+1; if i=7 then i:=0; j:=j+1; end if; if (clk' event and clk='1') then Bufftemp(2*j,2*i+1)<= Im(2*j,2*i+1) - 5; Buffsig<=Bufftemp(i,j); OutResult<=Buffsig; end if; end process;

I highly suggest reading books or tutorials on using VHDL for digital logic design. Here you have code that doesnt fit with normal templates. It may "work" in hardware as Quartus tends to let you get away with some poor coding styles, but your code will likely appear a but strange in simulation. 1. First of all, I highly suggest you only use signals for the time being, at least until you understand the consequences of using variables on your inferred hardware. 2. You i and j counters are not inside the clocked part of the process, so in simulation they will count on both the rising and falling edges of the clock, which is not possible in real hardware. This is because of the way VHDL works. These should be moved inside the rising edge clock part. 3. While it is not a "bad" thing, do you realise you have a 3 clock latency through the design? Have you tried to simulate this in a simulator? like modelsim?

--- Quote Start --- I highly suggest reading books or tutorials on using VHDL for digital logic design. Here you have code that doesnt fit with normal templates. It may "work" in hardware as Quartus tends to let you get away with some poor coding styles, but your code will likely appear a but strange in simulation. 1. First of all, I highly suggest you only use signals for the time being, at least until you understand the consequences of using variables on your inferred hardware. 2. You i and j counters are not inside the clocked part of the process, so in simulation they will count on both the rising and falling edges of the clock, which is not possible in real hardware. This is because of the way VHDL works. These should be moved inside the rising edge clock part. 3. While it is not a "bad" thing, do you realise you have a 3 clock latency through the design? Have you tried to simulate this in a simulator? like modelsim? --- Quote End --- Dear Moderator , I will consider all your points , Actually I read books for Pedroni and Pong about VHDL programming , I know I still have a lot to learn since I unconsciously back to sequential programming I used to utilize. About your notes, I will move the counters , this point I got it clearly. -- About signals , I will use them and hopefully you guide me to certain book that I can have better understanding. --Modelsim is not work often with my designs ! I am using Quartus ! Finally about the latency , I am thinking of unnecessary statement of signal assignment , but this will costs 1 clock cycle .. where is the other two? Dear, I am really appreciate your help and reply , I have designed an algorithm but I know I am unable to implement it well, as a consequence , each note you give will raise the implementation a lot. And I am ready to read any book you suggest Thanks again.

No logic elements although I have an output

26 Replies

Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
Your code still suggests you think you're writing software. You are not. You need to understand how the hardware works before you should be writing the code - hence why I suggest drawing a diagram.
I suggest reading how the ram works from here:

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ram.pdf
--- Quote End ---

Ok. I will .
Thank you.
Altera_Forum
Honored Contributor
8 years ago
Your code still suggests you think you're writing software. You are not. You need to understand how the hardware works before you should be writing the code - hence why I suggest drawing a diagram.
I suggest reading how the ram works from here:

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ram.pdf
Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
I highly suggest reading how memory works. You can only access 1 address per clock cycle. So if you really want to access 3 elements to add them, you will have to read them out over 3 clock cycles. You could pipeline the design to do the adds to minimise total latency.

I highly suggest using the megawizard ram, as this would become obvious.
--- Quote End ---

When I create a wizard I don't see how to connect it with my vhdl code in Pedroni book or in the document you sent me.
Also, I wonder if this way of reading in three clock cycles is efficient way
IF rising_edge(clock) THEN
i:=i+1;

reg1 <= ram1(i);
reg2<=reg1;
reg3<=reg2;
q1<=reg3;

Or you suggest me better one?
Thanks alot
Altera_Forum
Honored Contributor
8 years ago
I highly suggest reading how memory works. You can only access 1 address per clock cycle. So if you really want to access 3 elements to add them, you will have to read them out over 3 clock cycles. You could pipeline the design to do the adds to minimise total latency.

I highly suggest using the megawizard ram, as this would become obvious.
Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
Initially, you may do better using the mega wizard to generate the ram, then you know for sure that a ram will be used. Infered ram has to match the correct behavioural template to be correctly inferred, otherwise logic will be inferred.
Review this document for coding styles:
https://people.ece.cornell.edu/land/courses/ece5760/de1_soc/hdl_style_qts_qii51007.pdf
--- Quote End ---

Dear Admin,
I have created a memory ( but without wizard) and read it as follows
PROCESS (clock)
variable i:integer range -1 to 31:=-1;

BEGIN
IF rising_edge(clock) THEN
i:=i+1;

q1 <= ram1(i); -- output ( ram is mif file of 32 element, each of 3 bits)

END IF;
END PROCESS;

ram1 is external file that I successfully read its data , each element read in one clock cycle.
However , I am trying to get the first three elements after they read to apply a mathematical equation to them in next clock cycle. when I tried to create registers to carry the values , I unintentionally read three element at the same time so the memory transferred to logic elements.

My question is , How can I store only three elements and add them and then I get another three to add while keep reading? I tried to postponed in this way but am not sure if its true
BEGIN
IF rising_edge(clock) THEN
i:=i+1;

reg1 <= ram1(i);
reg2<=reg1;
reg3<=reg2;
q1<=reg3;
Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
Initially, you may do better using the mega wizard to generate the ram, then you know for sure that a ram will be used. Infered ram has to match the correct behavioural template to be correctly inferred, otherwise logic will be inferred.
Review this document for coding styles:
https://people.ece.cornell.edu/land/courses/ece5760/de1_soc/hdl_style_qts_qii51007.pdf
--- Quote End ---

I didn't call memory using mega wizard before , so I will read the document carefully and try it. I am really thankful to you. You are really helping me.
Altera_Forum
Honored Contributor
8 years ago
Initially, you may do better using the mega wizard to generate the ram, then you know for sure that a ram will be used. Infered ram has to match the correct behavioural template to be correctly inferred, otherwise logic will be inferred.
Review this document for coding styles:
https://people.ece.cornell.edu/land/courses/ece5760/de1_soc/hdl_style_qts_qii51007.pdf
Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
Quartus can infer internal hardware memory (RAM or ROM) from HDL code automatically without an explicit memory block instantiation. But the implemented memory function must be compatible with the properties of FPGA memory blocks. E.g. you can't access more than one respectively two (using the dual port feature) memory addresses within a clock cycle.

Your code in post# 9 is obviously not compatible with the memory inference rules.

Using the Quartus RAM and ROM templates assures that you're designing valid memory code.
--- Quote End ---

For no. 9 I will try to read them in buffer one by one. As I think , my code above consumes one each time. I tried to use the memory initialization written below with the code , but I still get the large number of logic element along with the memory. But I don't know if the large number because the input is not a RAM or because I am trying to output all the values mistakenly ?
BTW I am reading and revising your notes many times even after I reply to you.
This is the initialization M4K I used , if you have any notes to advice me ..
TYPE memory IS ARRAY (0 to 1023) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL myram: memory;
ATTRIBUTE ram_init_file: STRING;
ATTRIBUTE ramstyle: STRING;
ATTRIBUTE ramstyle OF myram: SIGNAL IS "M4K";
Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
Without the code, I cannot tell. I assume your code is not what you already posted?
Storing an image in logic will be very expensive. You really should use ram.
--- Quote End ---

I changed the code since as you advice me I can not fill same memory in two processes even if I am filling different locations. But I got the bigger problem of logic element localization. The new code is below , One process consumes 109 logic element!
Decompose array is an 8*8 array

LIBRARY ieee;
USE ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
USE work.my_data_types.all; -- to define array of input ( package )

ENTITY NewD IS
PORT (
clk: in std_logic;
bufftest:out signed(9 DOWNTO 0));

end NewD;

Architecture behave of NewD is
SIGNAL Im: Array2D:=(("0010000111","0001111110","0001001101","0001011011","0001101001","0001101011","0001101001","0001100111","0001101000","0001100000","0001110011","0010000100","0010001111","0010000000","0001100000","0001000100","0000000000"),
("0010000111","0001111010","0001001010","0001011001","0001100110","0001101000","0001110010","0010000001","0001101111","0001011100","0001101001","0010000011","0001111010","0010011000","0001000111","0000010010","0000000000"),
("0001100011","0001110111","0001000110","0001010110","0001011111","0001100001","0001110100","0010011100","0010101100","0001101111","0001100011","0001101001","0001110100","0001100000","0000011001","0000110101","0000000000"),
("0001001100","0001111000","0001000101","0001011000","0001011011","0001100011","0001111000","0010011111","0010110010","0010101111","0001111000","0001010000","0010000001","0000101100","0000100100","0001111100","0000000000"),
("0001010010","0001111100","0001000101","0001100000","0001100000","0001100110","0010000101","0010011000","0010011111","0010100100","0010011111","0010100011","0010100111","0000100101","0001011111","0010001000","0000000000"),
("0001010101","0010000000","0001000100","0001100100","0001110110","0001101001","0001101100","0001011111","0001100000","0010010011","0010101001","0010011100","0001010110","0000110011","0010000110","0010000011","0000000000"),
("0001010110","0001111111","0001000100","0001011001","0001111011","0001010111","0000110001","0000101001","0001110100","0010100100","0010000101","0001010000","0000011011","0001011101","0010001101","0010000011","0000000000"),
("0001010010","0010000000","0001001000","0001011011","0001011100","0000101010","0000100001","0001101100","0001111100","0010011100","0010000010","0000101110","0000100111","0001111101","0010000100","0001111010","0000000000"),
("0001001011","0010000010","0001001110","0001010111","0000111001","0000100100","0001001000","0001111001","0001100001","0010000011","0001010001","0000110000","0001000100","0010000100","0001111100","0010000100","0000000000"),
("0000111010","0010000000","0001010011","0001000000","0000101001","0000111000","0001010000","0001101110","0010001001","0010000011","0001100101","0000110001","0001100011","0001111110","0010000110","0010110000","0000000000"),
("0000111010","0010000100","0001001010","0000111000","0001000100","0001001110","0000101101","0001100111","0001110111","0010000001","0001000001","0000110111","0001111011","0001111000","0010011111","0010111101","0000000000"),
("0000110001","0010001000","0001000001","0000111001","0001011111","0000110010","0000011101","0001001001","0001110011","0001101010","0000011100","0001000011","0001111111","0001110110","0010101110","0010110001","0000000000"),
("0001000011","0010000010","0000110110","0000110001","0001010010","0000110011","0000011010","0000111100","0001110100","0010001101","0001100000","0001000101","0001101101","0001101000","0010100001","0001001100","0000000000"),
("0001010011","0010000010","0000101101","0000100000","0001000000","0001000111","0000100100","0001010001","0001110011","0010001100","0010110010","0001101011","0001110010","0010001110","0001111110","0001000100","0000000000"),
("0001001111","0010000100","0000101100","0000011011","0000110101","0000101011","0000110010","0001100010","0001110011","0001111100","0010101001","0010001111","0001001111","0010001001","0001010100","0000111110","0000000000"),
("0001011101","0010000100","0000100111","0000101001","0000110011","0000101000","0001001111","0001101101","0001110110","0001111000","0010010101","0010011111","0001001110","0001010111","0000111110","0000110110","0000000000"),
("0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000"));

signal DRP0sig:DecompArray;

begin

------ RP0
RP0: Process (clk)
variable i:integer range -1 to 8:=-1;
variable j:integer range 0 to 7:=0;
variable cntrr:integer range 0 to 256; -- THIS COUNTER I made to take one output each clock cycle

begin
if (clk' event and clk='1') then
i:=i+1;
if i>7 then
i:=0;
j:=j+1;
if j=8 then
j:=0;
end if;
end if;

DRP0sig(j,i)<= Im(2*j,2*i+1) - 5;-- to modify the image value

end if;

bufftest<=DRP0sig(cntrr,0); --show the first column of output

end process;
end behave;
Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
The number of logic elements are enormous ! is that because I have the entire image inside logic elements and I didn't utilize any memory ?
--- Quote End ---

Quartus can infer internal hardware memory (RAM or ROM) from HDL code automatically without an explicit memory block instantiation. But the implemented memory function must be compatible with the properties of FPGA memory blocks. E.g. you can't access more than one respectively two (using the dual port feature) memory addresses within a clock cycle.

Your code in post# 9 is obviously not compatible with the memory inference rules.

Using the Quartus RAM and ROM templates assures that you're designing valid memory code.

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No logic elements although I have an output

26 Replies

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