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Quartus can infer internal hardware memory (RAM or ROM) from HDL code automatically without an explicit memory block instantiation. But the implemented memory function must be compatible with the properties of FPGA memory blocks. E.g. you can't access more than one respectively two (using the dual port feature) memory addresses within a clock cycle.
Your code in post# 9 is obviously not compatible with the memory inference rules.
Using the Quartus RAM and ROM templates assures that you're designing valid memory code.
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For no. 9 I will try to read them in buffer one by one. As I think , my code above consumes one each time. I tried to use the memory initialization written below with the code , but I still get the large number of logic element along with the memory. But I don't know if the large number because the input is not a RAM or because I am trying to output all the values mistakenly ?
BTW I am reading and revising your notes many times even after I reply to you.
This is the initialization M4K I used , if you have any notes to advice me ..
TYPE memory IS ARRAY (0 to 1023) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL myram: memory;
ATTRIBUTE ram_init_file: STRING;
ATTRIBUTE ramstyle: STRING;
ATTRIBUTE ramstyle OF myram: SIGNAL IS "M4K";
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