No logic elements although I have an output

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I highly suggest reading how memory works. You can only access 1 address per clock cycle. So if you really want to access 3 elements to add them, you will have to read them out over 3 clock cycles. You could pipeline the design to do the adds to minimise total latency.

I highly suggest using the megawizard ram, as this would become obvious.

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When I create a wizard I don't see how to connect it with my vhdl code in Pedroni book or in the document you sent me.

Also, I wonder if this way of reading in three clock cycles is efficient way

IF rising_edge(clock) THEN

i:=i+1;

reg1 <= ram1(i);

reg2<=reg1;

reg3<=reg2;

q1<=reg3;

Or you suggest me better one?

Thanks alot