--- Quote Start ---
The number of logic elements are enormous ! is that because I have the entire image inside logic elements and I didn't utilize any memory ?
--- Quote End ---
Quartus can infer internal hardware memory (RAM or ROM) from HDL code automatically without an explicit memory block instantiation. But the implemented memory function must be compatible with the properties of FPGA memory blocks. E.g. you can't access more than one respectively two (using the dual port feature) memory addresses within a clock cycle.
Your code in post# 9 is obviously not compatible with the memory inference rules.
Using the Quartus RAM and ROM templates assures that you're designing valid memory code.
Honored Contributor
