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Altera_Forum
Honored Contributor
Honored ContributorNo logic elements although I have an output
Hello Please guide me why I don't see any logic element for the current code : LIBRARY ieee; USE ieee.std_logic_1164.all; Use ieee.numeric_std.all; USE work.my_data_types.all; -- to def...
Altera_ForumHonored Contributor
Honored ContributorI highly suggest reading how memory works. You can only access 1 address per clock cycle. So if you really want to access 3 elements to add them, you will have to read them out over 3 clock cycles. You could pipeline the design to do the adds to minimise total latency.
I highly suggest using the megawizard ram, as this would become obvious.
