Need help with timing constraints/closure for an EMIF design

Hi Richard,

Thanks for your help past few weeks. You can close this request.

Best,

Bharat

Thank you for the confirmation. Unfortunately, I don't have a script available that automatically converts async to sync. Users will need to write their own scripts to suit their specific design requirements.

With that, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

Thank you and have a great day!

Best Regards,

Richard Tan

By changing to the sclr port, it helps improve timing, bringing you a step closer to closing timing.

With that said, do you have any further inquiries regarding this case?

If not, I will proceed to transition this thread to community support.

Regards,

Richard Tan

Thanks Richard.

Best,

Bharat

I have checked with my team.

Unfortunately, the assignment can not change the aclr to sclr, you will need to change the code to use sclr port if possible.

Regards,

Richard Tan

Hi Richard,

Below are some messages I see in the fit report.

; Retiming Restrictions at Register #1: ;
; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_0|mc|mc_half_0|mc_ior_row|memory_controller_row|u_rs8_decode|gen_p3_pipe.handshaking_phase3|TX_data[46] ;
; Node uses an asynchronous clear port

; Retiming Restrictions at Register #1: ;
; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_1|mc|mc_half_0|mc_ior_row|memory_controller_row|u_rs8_decode|u_rs8_berl_l|handshaking_phaseA|TX_data[6]~RTM_41 ;
; Node uses an asynchronous clear port ;
; ;
; Retiming Restrictions at Register #2: ;
; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_1|mc|mc_half_0|mc_ior_row|memory_controller_row|u_rs8_decode|u_rs8_berl_l|handshaking_phase1|TX_data[53]~RTM_541 ;
; Node uses an asynchronous clear port ;

Below is a message from fit.fastforward.rpt

; Retiming Restrictions at Register #16: ;
; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_1|mc|mc_half_0|mc_ior_row|memory_controller_row|gen_rs8_pipe2.handshaking_pipeline_dec|TX_data[100]~RTM ;
; Node uses an asynchronous clear port

Those also form the path where I think the timing failures are. I did see many more messages earlier stating "cannot force asynchronous clear....". don't exactly remember the complete message. But with this build also I see timing failures for about 2.5 on 200MHz clock.

Best,

Bharat

I have compiled your design. Could you let me know which register that the Quartus does not force it to synchronous clear? I don't see it in the technology map viewer or perhaps I have overlook.

Regards,

Richard Tan

Hi Richard,

I have uploaded the design at the secure site you sent the information about. Please let me know if I can provide any further information.

Best,

Bharat

I have email you the instructions on how to securely upload your design.

Please check your email inbox.

Regards,

Richard Tan

HI Richard

I haven't yet converted the asynchronous reset to synchronous. I will get to it tomorrow.

I can share the archive of the design. Please let me know if I should upload it somewhere else or send to a any specific email address.

Best,

Bharat