Forum Discussion

Occasional Contributor

8 months ago

Need help with timing constraints/closure for an EMIF design

Hi, We have a design with 2 EMIFs with user clock at 200Mhz and it had more than 3.5 ns timing failure when the RS8 logic was added. With design changes and iterations the design still fails by 2ns....

ddr_.fit.fastforward.zip185 KB

ddr_u1.fit.fastforward.txt2.1 MB

ddr_u2.fit.fastforward.txt7.3 MB

Fpga Devkit

RichardT_altera

Super Contributor

6 months ago

I have compiled your design. Could you let me know which register that the Quartus does not force it to synchronous clear? I don't see it in the technology map viewer or perhaps I have overlook.

Regards,

Richard Tan

Forum Discussion

Need help with timing constraints/closure for an EMIF design

Recent Discussions

intel_onchip_Memory II RAM: r/w doesn t work from FPGA but from HPS

Power Rating Required for RZQ Resistor on Cyclone V SE

MAX 10. No 3.0 V Schmitt Trigger I/O standard

Arria 10: Remote Update may brick FPGA and Factory Fallback won't work

Unable to program EPCQ16A on custom cyclone IV board - error during jic flashing.