Forum Discussion
BKB
Occasional Contributor
Occasional ContributorNeed help with timing constraints/closure for an EMIF design
Hi, We have a design with 2 EMIFs with user clock at 200Mhz and it had more than 3.5 ns timing failure when the RS8 logic was added. With design changes and iterations the design still fails by 2ns....
BKBOccasional Contributor
Occasional ContributorHI Richard
I haven't yet converted the asynchronous reset to synchronous. I will get to it tomorrow.
I can share the archive of the design. Please let me know if I should upload it somewhere else or send to a any specific email address.
Best,
Bharat
