Need help with timing constraints/closure for an EMIF design

Hi Richard,

Below are some messages I see in the fit report.

; Retiming Restrictions at Register #1: ;
; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_0|mc|mc_half_0|mc_ior_row|memory_controller_row|u_rs8_decode|gen_p3_pipe.handshaking_phase3|TX_data[46] ;
; Node uses an asynchronous clear port

; Retiming Restrictions at Register #1: ;
; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_1|mc|mc_half_0|mc_ior_row|memory_controller_row|u_rs8_decode|u_rs8_berl_l|handshaking_phaseA|TX_data[6]~RTM_41 ;
; Node uses an asynchronous clear port ;
; ;
; Retiming Restrictions at Register #2: ;
; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_1|mc|mc_half_0|mc_ior_row|memory_controller_row|u_rs8_decode|u_rs8_berl_l|handshaking_phase1|TX_data[53]~RTM_541 ;
; Node uses an asynchronous clear port ;

Below is a message from fit.fastforward.rpt

; Retiming Restrictions at Register #16: ;
; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_1|mc|mc_half_0|mc_ior_row|memory_controller_row|gen_rs8_pipe2.handshaking_pipeline_dec|TX_data[100]~RTM ;
; Node uses an asynchronous clear port

Those also form the path where I think the timing failures are. I did see many more messages earlier stating "cannot force asynchronous clear....". don't exactly remember the complete message. But with this build also I see timing failures for about 2.5 on 200MHz clock.

Best,

Bharat