Forum Discussion
BKB
Occasional Contributor
Occasional ContributorNeed help with timing constraints/closure for an EMIF design
Hi, We have a design with 2 EMIFs with user clock at 200Mhz and it had more than 3.5 ns timing failure when the RS8 logic was added. With design changes and iterations the design still fails by 2ns....
RichardT_altera
Super Contributor
Super ContributorBy changing to the sclr port, it helps improve timing, bringing you a step closer to closing timing.
With that said, do you have any further inquiries regarding this case?
If not, I will proceed to transition this thread to community support.
Regards,
Richard Tan
BKBOccasional Contributor
Occasional ContributorThanks Richard. No, I don't have any specific inquiry except that if you have a script or function that can accept a file and convert all asynchronous to synchronous reset, that would help tremendously. I am having issues with the script I am trying, even with chatgpt.
you can transition this tread to community support.
Best,
Bharat
