Forum Discussion
BKB
Occasional Contributor
Occasional ContributorNeed help with timing constraints/closure for an EMIF design
Hi, We have a design with 2 EMIFs with user clock at 200Mhz and it had more than 3.5 ns timing failure when the RS8 logic was added. With design changes and iterations the design still fails by 2ns....
BKBOccasional Contributor
Occasional ContributorHi Richard,
I have uploaded the design at the secure site you sent the information about. Please let me know if I can provide any further information.
Best,
Bharat
