Forum Discussion
BKB
Occasional Contributor
Occasional ContributorNeed help with timing constraints/closure for an EMIF design
Hi, We have a design with 2 EMIFs with user clock at 200Mhz and it had more than 3.5 ns timing failure when the RS8 logic was added. With design changes and iterations the design still fails by 2ns....
RichardT_altera
Super Contributor
Super ContributorI have checked with my team.
Unfortunately, the assignment can not change the aclr to sclr, you will need to change the code to use sclr port if possible.
Regards,
Richard Tan
