Forum Discussion
BKB
Occasional Contributor
Occasional ContributorNeed help with timing constraints/closure for an EMIF design
Hi, We have a design with 2 EMIFs with user clock at 200Mhz and it had more than 3.5 ns timing failure when the RS8 logic was added. With design changes and iterations the design still fails by 2ns....
RichardT_altera
Super Contributor
Super ContributorThank you for the confirmation. Unfortunately, I don't have a script available that automatically converts async to sync. Users will need to write their own scripts to suit their specific design requirements.
With that, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.
The community users will be able to help you on your follow-up questions.
Thank you and have a great day!
Best Regards,
Richard Tan
