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BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
8 months ago

Need help with timing constraints/closure for an EMIF design

Hi,

We have a design with 2 EMIFs with user clock at 200Mhz and it had more than 3.5 ns timing failure when the RS8 logic was added. With design changes and iterations the design still fails by 2ns.

The fit.fastforward report makes some suggestions to add register stages which I have passed on the designers and waiting response.

The report also makes suggestions to change asynchronous clears to synchronous clears. I haven't made the changes in the code but I set it in qsf

set_global_assignment -name FORCE_SYNCH_CLEAR ON

But the the fit.fastforward report mentions that the asynchronous clear are not converted to synchronous. Please review the review report and help with timing closure.

Best,

BB

Fpga Devkit

23 Replies

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  • BKB's avatar
    BKB
    Icon for Occasional Contributor rankOccasional Contributor
    7 months ago

    Hi Richard,

    I have uploaded the design at the secure site you sent the information about. Please let me know if I can provide any further information.

    Best,

    Bharat

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    6 months ago

    I have compiled your design. Could you let me know which register that the Quartus does not force it to synchronous clear? I don't see it in the technology map viewer or perhaps I have overlook.


    Regards,

    Richard Tan


  • BKB's avatar
    BKB
    Icon for Occasional Contributor rankOccasional Contributor
    6 months ago

    Hi Richard,

    Below are some messages I see in the fit report.

    ; Retiming Restrictions at Register #1: ;
    ; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_0|mc|mc_half_0|mc_ior_row|memory_controller_row|u_rs8_decode|gen_p3_pipe.handshaking_phase3|TX_data[46] ;
    ; Node uses an asynchronous clear port

    ; Retiming Restrictions at Register #1: ;
    ; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_1|mc|mc_half_0|mc_ior_row|memory_controller_row|u_rs8_decode|u_rs8_berl_l|handshaking_phaseA|TX_data[6]~RTM_41 ;
    ; Node uses an asynchronous clear port ;
    ; ;
    ; Retiming Restrictions at Register #2: ;
    ; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_1|mc|mc_half_0|mc_ior_row|memory_controller_row|u_rs8_decode|u_rs8_berl_l|handshaking_phase1|TX_data[53]~RTM_541 ;
    ; Node uses an asynchronous clear port ;

    Below is a message from fit.fastforward.rpt

    ; Retiming Restrictions at Register #16: ;
    ; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_1|mc|mc_half_0|mc_ior_row|memory_controller_row|gen_rs8_pipe2.handshaking_pipeline_dec|TX_data[100]~RTM ;
    ; Node uses an asynchronous clear port

    Those also form the path where I think the timing failures are. I did see many more messages earlier stating "cannot force asynchronous clear....". don't exactly remember the complete message. But with this build also I see timing failures for about 2.5 on 200MHz clock.

    Best,

    Bharat

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    6 months ago

    I have checked with my team.

    Unfortunately, the assignment can not change the aclr to sclr, you will need to change the code to use sclr port if possible.


    Regards,

    Richard Tan


  • BKB's avatar
    BKB
    Icon for Occasional Contributor rankOccasional Contributor
    6 months ago

    Thanks Richard.

    Best,

    Bharat

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    6 months ago

    By changing to the sclr port, it helps improve timing, bringing you a step closer to closing timing.

    With that said, do you have any further inquiries regarding this case?

    If not, I will proceed to transition this thread to community support.

    Regards,

    Richard Tan

    • BKB's avatar
      BKB
      Icon for Occasional Contributor rankOccasional Contributor
      6 months ago

      Thanks Richard. No, I don't have any specific inquiry except that if you have a script or function that can accept a file and convert all asynchronous to synchronous reset, that would help tremendously. I am having issues with the script I am trying, even with chatgpt.

      you can transition this tread to community support.

      Best,

      Bharat

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    6 months ago

    Thank you for the confirmation. Unfortunately, I don't have a script available that automatically converts async to sync. Users will need to write their own scripts to suit their specific design requirements.


    With that, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

    The community users will be able to help you on your follow-up questions.


    Thank you and have a great day!


    Best Regards,

    Richard Tan



  • BKB's avatar
    BKB
    Icon for Occasional Contributor rankOccasional Contributor
    6 months ago

    Hi Richard,

    Thanks for your help past few weeks. You can close this request.

    Best,

    Bharat