Need help with a VIP design like the C5G example

Hi,

that all depend son your system-settings.

You said, your Clocked-Video-Output runs at 44.8MHz. This is the outgoing clock of the CVO? So the CVO is configured with two clock domains? The (let's call it) Stream-Clock and the Video-Clock. Right?

What color plane setting do you have? All transmitted in parallel, or in sequence? What are the burst-settings of the Frame-Reader? How wide is the Frame-Reader-Memory-Interface and is it clocked with the DDR-Clock or with the Avalon-Clock?

The minimum frequency depends on the settings of the Color-Plane-Sequencer.

The only question I could answer without knowing more about your system-setup is the question regarding the clock domains:

-All IPs you connect with Avalon Stream, in your case the whole pipeline have to have the same clock for their streaming-ports. In your case variable is the Clock for the Memory-Interface of the Frame-Reader and the outgoing clock of the CVO.

So please give us more details on what you need, and what you have build yet.

Kind regards

--- Quote Start ---

Hi,

that all depend son your system-settings.

You said, your Clocked-Video-Output runs at 44.8MHz. This is the outgoing clock of the CVO? So the CVO is configured with two clock domains? The (let's call it) Stream-Clock and the Video-Clock. Right?

What color plane setting do you have? All transmitted in parallel, or in sequence? What are the burst-settings of the Frame-Reader? How wide is the Frame-Reader-Memory-Interface and is it clocked with the DDR-Clock or with the Avalon-Clock?

The minimum frequency depends on the settings of the Color-Plane-Sequencer.

The only question I could answer without knowing more about your system-setup is the question regarding the clock domains:

-All IPs you connect with Avalon Stream, in your case the whole pipeline have to have the same clock for their streaming-ports. In your case variable is the Clock for the Memory-Interface of the Frame-Reader and the outgoing clock of the CVO.

So please give us more details on what you need, and what you have build yet.

Kind regards

--- Quote End ---

Thank you for taking the time to reply.

I was going to add screen shots but I don't know how. Anyway,

vip_vfr is configured as follows:

Bits per color planes 8

Planes in parallel 3

Number of colors in sequence 1

Image width 970

Image height 720

Master port width 32

FIFO depth 1024

Read master FIFO burst target 64

---

vip_itc:

Width 970

Height 720

Bits per pixel 8

Color planes 3

Parallel transmission format

Video in and out use the same clock NO (just discovered this option)

---

All IPs share a 44.8Mhz clock for now. This is probably wrong and I am

going to have to add a PLL and a vip_cpr. Why should I have a vip_cpr?

Thanks,

S.

Here are some screen shots of the configuration. Please make any suggestions.

Thanks,

S.

I added a PLL for the IPs. Now they all run at 120Mhz and the vip_itc output runs at 44.8 as is the master-bridge. I still have ONCHIP RAM

but I intend to switch to LPDDR. I can load patterns into RAM however, the only video I get is a blue screen after configuring/starting the Frame-Reader.

How should I configure the frame reader given the number above? what is the formulae for configuring the registers?

Thanks,

S.

Do you have the correct timings including Vsync, hsync and blanking for your Output-Video-Setting? Why 970x720? This is not a standard format, is it?

Where is your Frame Reader connected? On-Chip-RAM?

Could you please add pictures in higher resolution of the QSYS-System and the configuration? It hard to read them...

The ColorPlaneSequencer is there to put either the from serial color-plane-transmission to parallel or reversed...

Thanks Taz1984! Yes, the 970x720 is the display panel requirement.

The Frame-Reader is connected directly to the ONCHIP RAM which is way too small for what we need but for now its is easier to debug.

Here are some more details:

-When the Frame-reader is turned ON I do get video (blue screen)

-In simulation I can see the FR master read from RAM but JUST once the data that I wrote there and then stops.

-I do not have a Sequencer in the path between the FR and the ITC could that be the problem?

-Could the fact that my RAM is too small be the problem? why would the FR do just one access to RAM and stop?

-Could you provide a simple example of configuration of a FR in HW and configuration in SW?

-What about the bus widths of the RAM, Frame-Reader, Sequencer and itc? should they all be say 32b and should they match?

Thanks,

S.

Hi Guys,

I've attached more screen shots of my system. I added the LPDDR2, Sequences, a PLL to provide 120Mhz local IP clock. As before, I can R/W from all IPs

but not from the new LPDDR2. I followed the C5G example with all pin constraints, etc. The Clocked Video controller has its own 44.8Mhz from outside qsys.

Could someone look at my configuration and tell me if there is something wrong?

Thanks,

S.