Need help with a VIP design like the C5G example

Thanks Taz1984! Yes, the 970x720 is the display panel requirement.

The Frame-Reader is connected directly to the ONCHIP RAM which is way too small for what we need but for now its is easier to debug.

Here are some more details:

-When the Frame-reader is turned ON I do get video (blue screen)

-In simulation I can see the FR master read from RAM but JUST once the data that I wrote there and then stops.

-I do not have a Sequencer in the path between the FR and the ITC could that be the problem?

-Could the fact that my RAM is too small be the problem? why would the FR do just one access to RAM and stop?

-Could you provide a simple example of configuration of a FR in HW and configuration in SW?

-What about the bus widths of the RAM, Frame-Reader, Sequencer and itc? should they all be say 32b and should they match?

Thanks,

S.