Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Need help with a VIP design like the C5G example

Hi Guys, I put together simple LPDDR2+vip_vfr+vip_cpr+vip_itc system based on the C5G example for the StarterKit board. To keep the system simple I removed a number of IPs. Instead of th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi Guys,

I've attached more screen shots of my system. I added the LPDDR2, Sequences, a PLL to provide 120Mhz local IP clock. As before, I can R/W from all IPs

but not from the new LPDDR2. I followed the C5G example with all pin constraints, etc. The Clocked Video controller has its own 44.8Mhz from outside qsys.

Could someone look at my configuration and tell me if there is something wrong?

Thanks,

S.