Forum Discussion
Honored ContributorNCO help...
Hi i'm trying to test a fixed point filter on a FPGA board, my filter has an input of 16 bit, but the maximum value it can take without saturation is 1023 which is 11 bits. so far the only signal i've been using to is the NCO megafunction. when i set the NCO to have a magnitude of 16 bits i get severe distortion and loss of precision, i cant change the NCO to have a smaller number of bits or i get a bit mismatch, and i cant reduce the number of bits of the filter because i get distortion and loss of precision again. i'm using simulink and fixed point advisor in simulink to design this filter....
Can anyone please help..? not sure if there is another way to test the filter with a more dynamic signal. or if anyone is familiar with simulink how i can optimize my design.36 Replies
Altera_Forum--- Quote Start --- "Bus" and "Fsin_o1" are same nodes according to your diagram. Yet they show different values. I think you have set Fsin_o1 correctly to 2's complement but have set bus to sign and magnitude Regarding decimation/interpolation, I thought you are trying QMF filter bank. In that case you apply down transition after filter. Then you apply up transition before interpolation but you could be designing something else. The actual implementation of these transitions is required and there are two options to implement them: 1) you can do that explicitly i.e. discard every other sample after decimation filter. or add zero after every sample before interpolation. 2) you can assume discarding or adding zero and design your filter computation with that in mind. It gives equivalent results. --- Quote End --- If you look at this attachment i posted a few posts ago, you can see that the line chart looks completely different, the fsin_o looks right, but not the bus line. i am designing a QMF filter bank. The way i designed the filter was i used a matlab function called firpr2chfb(n, fp) <---designs four FIR filters for the analysis sections (h0 and h1) and synthesis section is (g0 and g1) of a two-channel perfect reconstruction filter bank. The design corresponds to the orthogonal filter banks also known as power-symmetric filter banks. fp is the passband edge frequency. and mfilt.firdecim(), mfilt.firinterp() which designs the decimator and interpolator. so the upsampling and filtering is internal. heres a link to get an idea of what i'm doing and how i'm doing it. ftp://www.ce.cmu.edu/hsuantuc/public/toolbox/filterdesign/filtdesdemos/html/pr2chfilterbankdemo.html- Altera_Forum
"Bus" and "Fsin_o1" are same nodes according to your diagram. Yet they show different values. I think you have set Fsin_o1 correctly to 2's complement but have set bus to sign and magnitude
Regarding decimation/interpolation, I thought you are trying QMF filter bank. In that case you apply down transition after filter. Then you apply up transition before interpolation but you could be designing something else. The actual implementation of these transitions is required and there are two options to implement them: 1) you can do that explicitly i.e. discard every other sample after decimation filter. or add zero after every sample before interpolation. 2) you can assume discarding or adding zero and design your filter computation with that in mind. It gives equivalent results. - Altera_Forum
Attached is what the wiring looks like..i followed an example Fvm posted, as u can see from that attachment Fsin_o is attached right at the input of the filter so it looked okay, but the bus which comes directly out of the NCO looks wierd. What i should expect is that the Fsin_o and The output should be the same or close. but clearly thats not the case.
Also attached is the subsystem is comprised of, as you can see from the labels it's 2 decimators entering 2 interpolators, because they operate at different frequencies i was wondering if i should place a rate transition in between blocks. the rate transition is a block that Handle transfer of data between ports operating at different rates. The tool i'm using to design this filter doesn't warn me of potential errors that might occur in hardware implementation. - Altera_Forum
When Fo = -3 your bus does not show negative value, instead it shows 2045
as if its sign bit is 0 instead of 1 thus your wiring doesn't look right. For interpolation/decimation you implement the rate conversion through filters. Ofcourse you need to convert the rates but you have to explain what do you mean by rate transitions. - Altera_Forum
Okay i see you're certainly right, i see that the Fsin_o does go from 1023 to -1024, but i see that the bus still going beyond 1023 (attached), could that possibly be the reason i'm not seeing my desired output? the last problem i can think of is that the subsystem is comprised of decimators and interpolators, because it's a multirate filter would i need to put rate transitions between each block for it work on the FPGA.
- Altera_Forum
You must look at values displayed as 2's complement only then make your judgment.
Since you have extra sign bit you will get false -2048 on 12 bits bus if viewed as sign and magnitude. 1111 1111 1111 means -2047 in sign and magnitude. 1100 0000 0000 means -1024 in 2's complement - Altera_Forum
Yes i am showing sign and magnitude, but regardless the magnitude shouldnt be even close to that value.
- Altera_Forum
Are you displaying values correctly? I think you have set it to sign and magnitude instead of 2's complement since the sine values suddenly dip max negative after positive section.
- Altera_Forum
Okay another problem, when i do it as you described the input signal swings between 1023 and -2042 when it should be swinging from 1023 to -1024. This is causing severe saturation. so how do i make it so it stays within the range of an 11 bits. i'm assuming the way to do this would be to use the 11 LSB instead of the 11 MSB. If you look at my attached document you can see that the bus line is only 11 bits i'm not even sure how its possible for the bus line to have a value passed 1023, the only thing i can think of is that it's not being treated as a signed number. please help.
- Altera_Forum
It should be seen as a sign extension example, driving the unused MSB lines with the sign bit, it's under the sassumption, that the imput signal is signed in 2s complement.
