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Altera_Forum's avatar
Altera_Forum
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14 years ago

NCO help...

Hi i'm trying to test a fixed point filter on a FPGA board, my filter has an input of 16 bit, but the maximum value it can take without saturation is 1023 which is 11 bits. so far the only signal i'v...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Okay another problem, when i do it as you described the input signal swings between 1023 and -2042 when it should be swinging from 1023 to -1024. This is causing severe saturation. so how do i make it so it stays within the range of an 11 bits. i'm assuming the way to do this would be to use the 11 LSB instead of the 11 MSB. If you look at my attached document you can see that the bus line is only 11 bits i'm not even sure how its possible for the bus line to have a value passed 1023, the only thing i can think of is that it's not being treated as a signed number. please help.