Honored Contributor
Honored ContributorAttached is what the wiring looks like..i followed an example Fvm posted, as u can see from that attachment Fsin_o is attached right at the input of the filter so it looked okay, but the bus which comes directly out of the NCO looks wierd. What i should expect is that the Fsin_o and The output should be the same or close. but clearly thats not the case.
Also attached is the subsystem is comprised of, as you can see from the labels it's 2 decimators entering 2 interpolators, because they operate at different frequencies i was wondering if i should place a rate transition in between blocks. the rate transition is a block that Handle transfer of data between ports operating at different rates. The tool i'm using to design this filter doesn't warn me of potential errors that might occur in hardware implementation.
