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Altera_Forum
Honored Contributor
14 years agoNCO help...
Hi i'm trying to test a fixed point filter on a FPGA board, my filter has an input of 16 bit, but the maximum value it can take without saturation is 1023 which is 11 bits. so far the only signal i'v...
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- "Bus" and "Fsin_o1" are same nodes according to your diagram. Yet they show different values. I think you have set Fsin_o1 correctly to 2's complement but have set bus to sign and magnitude Regarding decimation/interpolation, I thought you are trying QMF filter bank. In that case you apply down transition after filter. Then you apply up transition before interpolation but you could be designing something else. The actual implementation of these transitions is required and there are two options to implement them: 1) you can do that explicitly i.e. discard every other sample after decimation filter. or add zero after every sample before interpolation. 2) you can assume discarding or adding zero and design your filter computation with that in mind. It gives equivalent results. --- Quote End --- If you look at this attachment i posted a few posts ago, you can see that the line chart looks completely different, the fsin_o looks right, but not the bus line. i am designing a QMF filter bank. The way i designed the filter was i used a matlab function called firpr2chfb(n, fp) <---designs four FIR filters for the analysis sections (h0 and h1) and synthesis section is (g0 and g1) of a two-channel perfect reconstruction filter bank. The design corresponds to the orthogonal filter banks also known as power-symmetric filter banks. fp is the passband edge frequency. and mfilt.firdecim(), mfilt.firinterp() which designs the decimator and interpolator. so the upsampling and filtering is internal. heres a link to get an idea of what i'm doing and how i'm doing it. ftp://www.ce.cmu.edu/hsuantuc/public/toolbox/filterdesign/filtdesdemos/html/pr2chfilterbankdemo.html