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Honored Contributor
Honored ContributorNCO help...
Hi i'm trying to test a fixed point filter on a FPGA board, my filter has an input of 16 bit, but the maximum value it can take without saturation is 1023 which is 11 bits. so far the only signal i'v...
Altera_ForumHonored Contributor
Honored Contributor"Bus" and "Fsin_o1" are same nodes according to your diagram. Yet they show different values. I think you have set Fsin_o1 correctly to 2's complement but have set bus to sign and magnitude
Regarding decimation/interpolation, I thought you are trying QMF filter bank. In that case you apply down transition after filter. Then you apply up transition before interpolation but you could be designing something else. The actual implementation of these transitions is required and there are two options to implement them: 1) you can do that explicitly i.e. discard every other sample after decimation filter. or add zero after every sample before interpolation. 2) you can assume discarding or adding zero and design your filter computation with that in mind. It gives equivalent results.
