Altera_Forum
Honored Contributor
7 years agoMonitor wires inside module region ModelSim in gate -level or timing simulation
While doing gate-level simulation, i found an output miss-match in my design. I want to investigate it further but all the wire in module.vo files, that was previously assigned in module.v, was renamed. My design is quite big, I have to monitor around 4 1000-bit bus wires to investigate this error. Since the bus wires is vast, it is not possible to temporarily assign those wires as output wires. Are there any way to monitor 4 1000-bit bus wire in timing simulation? For more information, I use Quartus Prime 17.1.0 and ModelSim Intel FPGA 10.5b.