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Altera_Forum
Honored Contributor
Honored ContributorMonitor wires inside module region ModelSim in gate -level or timing simulation
While doing gate-level simulation, i found an output miss-match in my design. I want to investigate it further but all the wire in module.vo files, that was previously assigned in module.v, was renam...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I am sorry for the messy reply before. I am new in this forum Do you man this panel(attached)? If it is the right panel, I am still confused by the renaming problem. https://www.alteraforum.com/forum/attachment.php?attachmentid=14878 --- Quote End --- Yes, that's the panel I was referring to.
